【SerDes】美信GMSL2-CSI调试心得

美信加解串器家族

美信（Maxim Integrated，现为 Analog Devices 旗下）的 GMSL2（Gigabit Multimedia Serial Link 第二代） 加串器（Serializer）与解串器（Deserializer）芯片家族广泛应用于 高级驾驶辅助系统（ADAS）、车载摄像头、工业视觉、环视系统、驾驶员监控系统（DMS）等场景 。这些芯片支持高带宽视频传输、长距离电缆连接（同轴或STP）、双向控制通道、功能安全（如 ASIL-B）等特性。

Serializer – Camera/adas盒子 端

1.max96717/max96717f

2.max9295/max9295D

Deserializer – 主控端(Soc侧)

1.Max96724/Max96724R

2.Max9296/Max9296A

Demo平台

简化框图：

Soc 读写解串器命令：

# ccidbgr:IIC调试应用   2:CCI节点2  0x27(Des 7Bit CCI addr)  0x0a:读取Des上的寄存器地址  3:以0x0a为起始地址，连读3个寄存器
ccidbgr 2 0x27 read21 0x0a 3
# 将0x06寄存器写成0xff
ccidbgr 2 0x27 write21 0x06 0xff

Bring up Camerr调试步骤

1.加串端输出参数收集

GMSL协议 - GMSL1/GMSL2

GMSL速率 - 3G/6G

GMSL传输模式 - TUNNEL/PIXEL
PIXEL ： 需要配置mapping关系
TUNNEL ： 视频数据透传

Camera输出图像格式 - YUV422/RGB888

加串输出分辨率

加串输出帧率

远端加串器型号

2.Link locK确认

Link Lock是Ser - Des之前物理链路链路是否通畅的表现方式，如果存在则表示解串已经识别到了加串器的接入，如果不存在则表明GMSL2物理链路不通，可能原因：

1.GMSL2协议不匹配 - 比如解串配成了GMSL2,Camera端加串输出的是GMSL1
2.GMSL2速率不匹配 - 比如Camera加串输出速率为6G,而解串器配的3G
3.Camera模模块供电有问题，不是POC供电，需要单独供电
4.线束问题

以max96724寄存器为例

ccidbgr 2 0x27 read21 0x0a   Link B Link lock，正常应为0xc8
ccidbgr 2 0x27 read21 0x0b   Link C Link lock，正常应为0xc8
ccidbgr 2 0x27 read21 0x0c   Link D Link lock，正常应为0xc8 
ccidbgr 2 0x27 read21 0x1a   Link A Link lock, bit3 = 1

common settting

// 格式(regaddr regdata delay)
 {
   /*gmsl 2*/
   {0x0010, 0x11, 0 },    // GMSL2  3G
   {0x0011, 0x11, 0 },    // GMSL2 3G
   /*csi output disable*/
   { 0x040B, 0x00, 0},
   { 0x0458, 0x00, 0},
   /*Disable GMSL2 all link I2C(Port0/1) remote control channel*/
   { 0x0003, 0xFF, 0},
   /*enable pipe 0 1 2 3*/
   { 0x00F4, 0x0F, 0},
   /*mipi phy 2x4*/
   { 0x08A0, 0x04, 0},
   /*mipi phy mapping*/
   { 0x08A3, 0xE4, 0},
   { 0x08A4, 0xE4, 0},
   /*mipi 4 data lane*/
   { 0x090A, 0xC0, 0},
   { 0x094A, 0xC0, 0},
   { 0x098A, 0xC0, 0},
   { 0x09CA, 0xC0, 0},
   /*enable mipi phy 0 1 2 3*/
   { 0x08A2, 0xF0, 0},
   /*mipi phy 0 1 data rate 1Ghz*/
   { 0x0415, 0x36, 0},
   { 0x0418, 0x36, 0},
   { 0x0007, 0x00, 0 },
};

specify_settings

{
    .video_pipe_sel = {
        {0x00F0, 0x00, 0}, {0x00F1, 0x00, 0}},
    .yuv_mux_mode = {
        {0x041A, 0xF0, 0}},  //Default enable YUV_8_10 MUX mode
    .soft_dt_bpp = {
        {0x040E, 0x5E, 0}, {0x040F, 0x7E, 0}, {0x0410, 0x7A, 0},   //Default dt as YUV422
        {0x040B, 0x00, 0}, {0x0411, 0x48, 0}, {0x0412, 0x20, 0}},  //Default bpp as YUV422
    .him_hvsrc_dbl_bws_de = {
        {0x0B06, 0xEF, 0}, {0x0C06, 0xEF, 0}, {0x0D06, 0xEF, 0}, {0x0E06, 0xEF, 0},  //Default HIM on, Auto determine the source of HSYNC/VSYNC
        {0x0B07, 0x84, 0}, {0x0C07, 0x84, 0}, {0x0D07, 0x84, 0}, {0x0E07, 0x84, 0},  //Default BWS=0, DBL=1, HVEN=1
        {0x0B0F, 0x01, 0}, {0x0C0F, 0x01, 0}, {0x0D0F, 0x01, 0}, {0x0E0F, 0x01, 0}}, //Default Disable HS/DE processing
};

3.Camera模块Pclk确认

pclk是Camera模块的时钟信号，可以通过pclk是否存在来判断Camera是否在输出图像，可以通过解串的反控IIC接口来反向读取加串器的pclk寄存器

ccidbgr 2 0x50 read21 0x112   回读远端Camera的Pclk，pclk存在，bit7应为1
ccidbgr 2 0x51 read21 0x112   回读远端Camera的Pclk，pclk存在，bit7应为1
ccidbgr 2 0x52 read21 0x112   回读远端Camera的Pclk，pclk存在，bit7应为1
ccidbgr 2 0x53 read21 0x112   回读远端Camera的Pclk，pclk存在，bit7应为1

一般max96724可以接4个Camera模块，它们的IIC地址可以都是0x80，所以在主机启动初始化的时候，需要将4路Camera重新alias一下它们的IIC地址，向加串的0x00写入alias后的地址。以上地址是将加串按顺序从0xa0开始alias后的地址

加串器配置demo(具体需跟Camera供应商核对)

    { 0x330, 0x00, 0 },
    /*4Lanes,Disable deskew,disable extended VC*/
    { 0x331, 0x30, 0 },
    /*Enable DT,DT=0x1E(yuv422_8bit)*/
    { 0x318, 0x5E, 0 },

4.Video Lock确认

Video Lock是判断Camera模块的视频数据是否输出到解串，并被解串lock住的标志，如果解串上读不到说明解串上没有正确解析到视频流，需要核对以下关键点

ccidbgr 2 0x27 read21 0x108   Link A Video lock，正常应为0x62
ccidbgr 2 0x27 read21 0x11a   Link B Video lock，正常应为0x62
ccidbgr 2 0x27 read21 0x12c   Link C Video lock，正常应为0x62
ccidbgr 2 0x27 read21 0x13e   Link D Video lock, 正常应为0x62

4.1 pixel Mode

像素模式会移除CSI-2的头部和尾部信息，仅对数据进行分包处理。数据类型（DT）或虚拟通道（VC）将作为独立的信息帧发送。串行器会在分包的视频行或数据帧中添加循环冗余校验（CRC），并将包含传感器数据、控制数据及CRC的最终帧通过GMSL链路传输。该机制为不同数据类型的分组方式提供了灵活性，并优化了GMSL链路的带宽利用率。解串器接收传感器数据后，将分别重建头尾信息、ECC校验及CRC校验，从而复现串行器接收的原始CSI-2数据。像素模式支持以下数据类型：RAW8/10/12/14/16/20、RGB565/666/888、YUV422 8/10位、用户自定义及通用长数据包类型。D-PHY最多支持16个虚拟通道，而C-PHY支持32个虚拟通道。

3mapping_settings Reg Demo

    {0x090B, 0x07, 0},  //Enable 3 mappings for pipeline 0
    {0x092D, 0x15, 0},  //Map to destination controller 1
    {0x090D, 0x1E, 0},  //Source data type(0x1E YUV422) and VC(0)
    {0x090E, 0x1E, 0},  //Destination dt(0x1E YUV422) and vc(0)
    {0x090F, 0x00, 0},  //Source dt(0x00 frame start) and vc(0)
    {0x0910, 0x00, 0},  //Destination dt(0x00 frame start) and vc(0)
    {0x0911, 0x01, 0},  //Source dt(0x01 frame end) and vc(0)
    {0x0912, 0x01, 0},  //Destination dt(0x01 frame end) and vc(0)
    {0x094B, 0x07, 0},  //Enable 3 mappings for pipeline 1
    {0x096D, 0x15, 0},  //Map to destination controller 1
    {0x094D, 0x1E, 0},  //Source data type(0x1E YUV422) and VC(0)
    {0x094E, 0x5E, 0},  //Destination dt(0x1E YUV422) and vc(1)
    {0x094F, 0x00, 0},  //Source dt(0x00 frame start) and vc(0)
    {0x0950, 0x40, 0},  //Destination dt(00 frame start) and vc(1)
    {0x0951, 0x01, 0},  //Source dt(0x01 frame end) and vc(0)
    {0x0952, 0x41, 0},  //Destination dt(0x01 frame end) and vc(1)
    {0x098B, 0x07, 0},  //Enable 3 mappings for pipeline 2
    {0x09AD, 0x15, 0},  //Map to destination controller 1
    {0x098D, 0x1E, 0},  //Source data type(0x1E YUV422) and VC(0)
    {0x098E, 0x9E, 0},  //Destination dt(0x1E YUV422) and vc(2)
    {0x098F, 0x00, 0},  //Source dt(0x00 frame start) and vc(0)
    {0x0990, 0x80, 0},  //Destination dt(0x00 frame start) and vc(2)
    {0x0991, 0x01, 0},  //Source dt(0x01 frame end) and vc(0)
    {0x0992, 0x81, 0},  //Destination dt(0x01 frame end) and vc(2)
    {0x09CB, 0x07, 0},  //Enable 3 mappings for pipeline 3
    {0x09ED, 0x15, 0},  //Map to destination controller 1
    {0x09CD, 0x1E, 0},  //Source data type(0x1E YUV422) and VC(0)
    {0x09CE, 0xDE, 0},  //Destination dt(0x1E YUV422) and vc(3)
    {0x09CF, 0x00, 0},  //Source dt(0x00 frame start) and vc(0)
    {0x09D0, 0xC0, 0},  //Destination dt(0x00 frame start) and vc(3)
    {0x09D1, 0x01, 0},  //Source dt(0x01 frame end) and vc(0)
    {0x09D2, 0xC1, 0},  //Destination dt(0x01 frame end) and vc(3)

4.2 tunnel Mode

在隧道模式下，包含ECC字节和CRC字节的CSI-2数据包头与数据包尾将与数据包数据一同通过GMSL链路原样传输。由于该模式完整保留了视频源的CSI-2 ECC和CRC校验机制，因此是安全关键型应用的推荐传输模式——此类应用对端到端数据完整性要求极高。在此模式下，设备仅与支持隧道模式的GMSL解串器进行接口连接。

与加串输出侧核对stream id,解串要配置和加串输出的同样的stream id(一般默认id是stream id 2，对应到解串是PipeZ)。

写入Common setting和link enable基本就可以了

4.4 fsync 方式

内同步：

由Camera模块中的加串器发送同步信号给sensor,无需解串器提供

外同步：

可以由GPIO通过解串路由到加串触发帧同步

由解串内部生成同步信号到加串触发帧同步

CCI也可以作为外部帧同步的触发

fsync_setting,由解串生成帧同步的寄存器配置demo

    {0x04A0, 0x34, 0},  //Frame sync generation is on. GPIO is used as FSYNC output and drives a slave device，Manual Mode
    {0x04AF, 0xCF, 0},  //Uses crystal oscillator clock for generating frame sync signal, Selects GMSL1 type of FSYNC signal to output from GPIO
    {0x04B1, 0x38, 0},  //GPIO ID 7 associated with GMSL2 FSYNC transmission(0x40 ID:8)
    {0x04A2, 0x50, 0},  //video 2 Master link select for frame sync generation，选择Pipe2为主链路，同步信号提前0.85us
    {0x04AA, 0x00, 0},
    {0x04AB, 0x00, 0},
    {0x04A7, 0x0C, 0},  //default 30fps
    {0x04A6, 0xB7, 0},  //default 30fps
    {0x04A5, 0x35, 0},  //default 30fps
    {0x04B7, 0x80, 0},
    {0x0B08, 0x10, 0},  //Enables frame sync signal transmission
    {0x0C08, 0x10, 0},  //Enables frame sync signal transmission
    {0x0D08, 0x10, 0},  //Enables frame sync signal transmission
    {0x0E08, 0x10, 0},  //Enables frame sync signal transmission

5.使能Link

需要先对Link 进行复位，然后在使能4路link

link_enable_settings

    {0x0018, 0x0F, 60000},      # reset Link
    {0x0006, 0xff, 250000 },    # Enable Link

6.soc取流

使用soc平台测试工具对解串器取流

start stream时需要对解串写

start_array

{0x40b,0x00,0}    // disable csi
{0x8a2,0xf4,0}    // Puts phy into normal mode
{0x40b,0x02,0}    // enable csi

停止取流的时需要对解串写

stop_array

{0x8a2,0x04,0}    // Puts phy into standby mode
{0x40b,0x00,0}    // disable csi

Bring up adas盒子

一般来说外置adas盒子会用于专门处理Camera,Lidar等传感器数据，并将环视图像bypass到座舱域用作AVM图像，这种情况下外置adas盒子会自己配置加串器，座舱侧解串也无法通过远控IIC操作加串器。

adas盒子的图像输出方式一般有两种，一种是由adas域拼接后，以一路link一个vc的方式将拼接好的一路视频流，bypass输出到到座舱与，另一种是1路link4路vc的方式传输4路视频流bypass到座舱。调试方式与bring up Camera步骤相似，只是步骤2pclk的确认需要登录进adas域对加串器读取pclk确认时钟输出。

Bring up Colorbar测试板

在生产环境内，一般会采用加串测试板来测试解串的功能是否正常，测试原理是解串器上接上4路加串器，写入寄存器配置，让加串器生成colorbar彩条，传输到解串上，soc从解串取流显示。

Colorbar模式下解串的配置Demo

    {0x0013, 0x75, 10000},
    {0x0007, 0x00, 0},
    {0x0003, 0x55, 10000},
    {0x0006, 0xff, 150000},
    {0x04B7, 0x80, 0},
    {0x0017, 0x14, 0},
    {0x0019, 0x94, 10000},
    {0x06C2, 0x10, 0},
    {0x14D1, 0x03, 0},
    {0x15D1, 0x03, 0},
    {0x16D1, 0x03, 0},
    {0x17D1, 0x03, 0},
    {0x0903, 0x00, 0},
    {0x0943, 0x00, 0},
    {0x0983, 0x00, 0},
    {0x09C3, 0x00, 0},
    {0x040B, 0x00, 0},
    {0x0010, 0x11, 0},
    {0x0011, 0x11, 0},
    {0x00F0, 0x62, 0},
    {0x00F1, 0xEA, 0},
    {0x00F4, 0x0F, 0},
    {0x040C, 0x00, 0},
    {0x040D, 0x00, 0},
    {0x040E, 0xA4, 0},
    {0x040F, 0x94, 0},
    {0x0410, 0x90, 0},
    {0x0411, 0xD8, 0},
    {0x0412, 0x60, 0},
    {0x090B, 0x07, 0},
    {0x092D, 0x15, 0},
    {0x090D, 0x24, 0},  //Source data type(0x1E RGB88) and VC(0)
    {0x090E, 0x24, 0},  //Destination dt(0x1E RGB88) and vc(0)
    {0x090F, 0x00, 0},  //Source dt(0x00 frame start) and vc(0)
    {0x0910, 0x00, 0},  //Destination dt(0x00 frame start) and vc(0)
    {0x0911, 0x01, 0},  //Source dt(0x01 frame end) and vc(0)
    {0x0912, 0x01, 0},  //Destination dt(0x01 frame end) and vc(0)
    {0x094B, 0x07, 0},  //Enable 3 mappings for pipeline 1
    {0x096D, 0x15, 0},  //Map to destination controller 1
    {0x094D, 0x24, 0},  //Source data type(0x1E RGB88) and VC(0)
    {0x094E, 0x64, 0},  //Destination dt(0x1E RGB88) and vc(1)
    {0x094F, 0x00, 0},  //Source dt(0x00 frame start) and vc(0)
    {0x0950, 0x40, 0},  //Destination dt(00 frame start) and vc(1)
    {0x0951, 0x01, 0},  //Source dt(0x01 frame end) and vc(0)
    {0x0952, 0x41, 0},  //Destination dt(0x01 frame end) and vc(1)
    {0x098B, 0x07, 0},  //Enable 3 mappings for pipeline 2
    {0x09AD, 0x15, 0},  //Map to destination controller 1
    {0x098D, 0x24, 0},  //Source data type(0x1E RGB88) and VC(0)
    {0x098E, 0xA4, 0},  //Destination dt(0x1E RGB88) and vc(2)
    {0x098F, 0x00, 0},  //Source dt(0x00 frame start) and vc(0)
    {0x0990, 0x80, 0},  //Destination dt(0x00 frame start) and vc(2)
    {0x0991, 0x01, 0},  //Source dt(0x01 frame end) and vc(0)
    {0x0992, 0x81, 0},  //Destination dt(0x01 frame end) and vc(2)
    {0x09CB, 0x07, 0},  //Enable 3 mappings for pipeline 3
    {0x09ED, 0x15, 0},  //Map to destination controller 1
    {0x09CD, 0x24, 0},  //Source data type(0x1E RGB88) and VC(0)
    {0x09CE, 0xE4, 0},  //Destination dt(0x1E RGB88) and vc(3)
    {0x09CF, 0x00, 0},  //Source dt(0x00 frame start) and vc(0)
    {0x09D0, 0xC0, 0},  //Destination dt(0x00 frame start) and vc(3)
    {0x09D1, 0x01, 0},  //Source dt(0x01 frame end) and vc(0)
    {0x09D2, 0xC1, 0},  //Destination dt(0x01 frame end) and vc(3)
    {0x08A0, 0x04, 0},  /*mipi phy 2x4*/
    {0x08A3, 0xE4, 0},  /*mipi phy mapping*/
    {0x08A4, 0xE4, 0},  /*mipi phy mapping*/
    {0x090A, 0xC0, 0},  /*mipi 4 data lane*/
    {0x094A, 0xC0, 0},  /*mipi 4 data lane*/
    {0x098A, 0xC0, 0},  /*mipi 4 data lane*/
    {0x09CA, 0xC0, 0},  /*mipi 4 data lane*/
    {0x08A2, 0xF0, 0},  /*enable mipi phy 0 1 2 3*/
    {0x1C00, 0xF4, 0},
    {0x1D00, 0xF4, 0},
    {0x1E00, 0xF4, 0},
    {0x1F00, 0xF4, 0},
    {0x0415, 0xEC, 0},   /*mipi phy 0 1 data rate 1Ghz*/
    {0x0418, 0xEC, 0},   /*mipi phy 0 1 data rate 1Ghz*/
    {0x041B, 0x34, 0},
    {0x041E, 0x34, 0},
    {0x04AF, 0xc0, 0},   // Video Pipe 1 in frame sync genertion   0x80&0xc0
    {0x1C00, 0xF5, 0},
    {0x1D00, 0xF5, 0},
    {0x1E00, 0xF5, 0},
    {0x1F00, 0xF5, 0},
    {0x0018, 0x0F, 100000},

Q&A

1.当解串上可以读到video lock，但是soc取流工具取不到流，比如qcarcam_test取流是freeze状态

可以尝试在取流时，读取以下寄存器，判断解串的phy是否在输出数据

#  ccidbgr 2 0x27 read21 0x8d0 5
0x8d0 -> 0x60
0x8d1 -> 0x0
0x8d2 -> 0x33
0x8d3 -> 0x0
0x8d4 -> 0xf0
#  ccidbgr 2 0x27 read21 0x8d0 5
0x8d0 -> 0x90
0x8d1 -> 0x0
0x8d2 -> 0xee
0x8d3 -> 0x0
0x8d4 -> 0xf0

有值在跳动，说明解串的mipi phy上数据正在输出，下一步可以排查取流的vc和mapping后的vc是否一致？或soc连接解串的phy和正在输出的phy是否一致？
如果不跳说明解串内部的video pipe可能和mipi phy映射关系不对，需要排查pipeline映射配置

如何检查soc的mipi是否有数据呢？
在取流的时候多次读取以下寄存器in32 0xAC84240，如果有值跳动则说明soc的mipi上是有收到数据的

如果此时qcarcam_test仍然取不到视频流，需要先排查驱动配置，检查log,没有报错，确认驱动配置无误的话考虑VS极性的问题

最近遇到一个问题，解串video lock，解串phy count，soc mipi count,驱动log都无问题，但qcarcam_test取流就是freeze的状态，排查后发现，是加串端VS极性的问题，加串端是低电平有效输出的，但是美信要求是高电平有效，所以调整max96724的CROSS_VS,根据加串接入的pipe编号，将bit6置1，比如：如果加串接在pipe3上，那就将0x239的bit6置1，qcarcam_test就取到视频流了。